SC15 Panel Line-Up for Nov. 19th

Asynchronous Many-­Task Programming Models for Next Generation Platforms

Next generation platform architectures will require us to fundamentally rethink our programming models and environments due to a combination of factors including extreme parallelism, data locality issues, and resilience. As seen in the computational sciences community, asynchronous many-task (AMT) programming models and runtime systems are emerging as a leading new paradigm.

While there are some overarching similarities between existing AMT systems, the community lacks consistent 1) terminology to describe runtime components, 2) application- and component-level interfaces, and 3) requirements for the lower level runtime and system software stacks.

This panel will engage a group of community experts in a lively discussion on status and ideas to establish best practices in light of requirements such as performance portability, scalability, resilience, and interoperability. Additionally, we will consider the challenges of user-adoption, with a focus on the issue of productivity, which is critical given the application code rewrite required to adopt this approach.

Moderator/Panelist Details:

• Robert Clay (Moderator) - Sandia National Laboratories
• Alex Aiken - Stanford University
• Martin Berzins - University of Utah
• Matthew Bettencourt - Sandia National Laboratories
• Laxmikant Kale - University of Illinois at Urbana-Champaign
• Timothy Mattson - Intel Corporation
• Lawrence Rauchwerger - Texas A&M University
• Vivek Sarkar - Rice University
• Thomas Sterling - Indiana University
• Jeremiah Wilke - Sandia National Laboratories

 

Towards an Open Software Stack for Exascale Computing

The panel will discuss what an open software stack should contain, what would make it feasible and what is not looking possible at the moment. The discussion is inspired by the fact that "this time, we have time" before the hardware actually reaches the market after 2020, so we can work on a software stack accordingly.

We will cover questions such as: Which would be the software development costs? What industries will migrate first? Would a killer app accelerate this process? Do we focus on algorithms to save power? How heterogeneous would/should “your” exascale system be? Is there a role for Co-design towards exascale? Is the Square Kilometre Array (SKA) project an example to follow? Would cloud computing be possible for exascale? Who will “own” the exascale era?

Moderator/Panelist Details:

• Nicolás Erdödy (Moderator) - Open Parallel Ltd.
• Pete Beckman - Argonne National Laboratory
• Chris Broekema - Netherlands Institute for Radio Astronomy
• Jack Dongarra - University of Tennessee
• John Gustafson - Ceranovo, Inc.
• Thomas Sterling - Indiana University
• Robert Wisniewski - Intel Corporation

 

Procuring Supercomputers: Best Practices and Lessons Learned

Procuring HPC systems is a challenging process of acquiring the most suitable machine under technical and financial constrains aiming at maximizing the benefits to the users’ applications and minimizing the risks during its lifetime.

In this panel, HPC leaders will discuss and debate on keys requirements and lessons learned for successful procurements of supercomputers.

How do we define the requirements of the system? Is it to acquire a system for maximizing the capacity and capability, assessing new/future technologies, deliver a system designed for specific applications or provide an all-purpose solution to a broad range of applications? Is the system just a status symbol or must it do useful work?

This panel will give the audience an opportunity to ask questions to panelists who are involved in the procurement of leadership-class supercomputers and capturing lessons learned and turning that hindsight into best practices to procure and the most suitable HPC system.

Moderator/Panelist Details:

• Bilel Hadri (Moderator) - King Abdullah University of Science and Technology
• Katie Antypas - National Energy Research Scientific Computing Center
• Bill Kramer - University of Illinois at Urbana-Champaign
• Satoshi Matsuoka - Tokyo Institute of Technology
• Greg Newby - Compute Canada
• Owen Thomas - Red Oak Consulting

SC15 Panel Line-Up for Nov. 18th

Supercomputing and Big Data: From Collision to Convergence

As data intensive science emerges, the need for high performance computing (HPC) to converge capacity and capabilities with Big Data becomes more apparent and urgent. Capacity requirements have stemmed from science data processing and the creation of large scale data products (e.g., earth observations, Large Hadron Collider, square-kilometer array antenna) and simulation model output (e.g., flight mission plans, weather and climate models).

Capacity growth is further amplified by the need for more rapidly ingesting, analyzing, and visualizing voluminous data to improve understanding of known physical processes, discover new phenomena, and compare results.

• How does HPC need to change in order to meet these Big Data needs?
• What can HPC and Big Data communities learn from each other?
• What impact will this have on conventional workflows, architectures, and tools?

An invited international panel of experts will examine these disruptive technologies and consider their long-term impacts and research directions.

Moderator/Panelist Details:

• George O. Strawn (Moderator) - Networking and Information Technology Research and Development National Coordination Office
• David Bader - Georgia Institute of Technology
• Ian Foster - University of Chicago
• Bruce Hendrickson - Sandia National Laboratories
• Randy Bryant - Executive Office of the President, Office of Science and Technology Policy
• George Biros - The University of Texas at Austin
• Andrew W. Moore - Carnegie Mellon University

Mentoring Undergraduates Through Competition

SC14 Group Photo of the SCC Teams

The next generation of HPC talent will face significant challenges to create software ecosystems and optimally use the next generation of HPC systems. The rapid advances in HPC make it difficult for academic institutions to keep pace.

The Student Cluster Competition (SCC), now in its ninth year, was created to address this issue by immersing students into all aspects of HPC. This panel will examine the impact of the SCC on the students and schools that have participated.

Representatives from five institutions from around the world will talk about their experiences with the SCC with regards to their students' career paths, integration with curriculum and academic HPC computing centers.

The panel will further discuss whether "extracurricular" activities, such as the SCC, provide sufficient return on investment and what activities could change or replace the competition to meet these goals more effectively.

Moderator/Panelist Details:

• Brent Gorda (Moderator) - Intel Corporation
• Jerry Chou - Tsinghua University
• Rebecca Hartman-Baker - Lawrence Berkeley National Laboratory
• Doug Smith - University of Colorado Boulder
• Xuanhua Shi - Huazhong University of Science and Technology
• Stephen Lien Harrell - Purdue University 

 

Programming Models for Parallel Architectures and Requirements for Pre-Exascale

Relying on domain scientists to provide programmer intervention to develop applications to emerging exascale platforms is a real challenge. A scientist prefers to express mathematics of the science, not describe the parallelism of the implementing algorithms.

Do we expect too much of the scientist to code for high parallel performance given the immense capabilities of the platform. This ignores that the scientist may have a mandate to code for a new architecture, and yet preserve portability in their code.

This panel will bring together user experience, programming model, architecture experts to discuss the pressing needs in finding the path forward to port scientific codes to such a platform. We hope to discuss the evolving programming stack, application-level requirements, and address the hierarchical nature of large systems in terms of different cores, memory levels, power consumption and the pragmatic advances of near term technology.

Moderator/Panelist Details:

• Fernanda Foertter (Moderator) - Oak Ridge National Laboratory
• Barbara Chapman - University of Houston
• Steve Oberlin - NVIDIA Corporation
• Satoshi Matsuoka - Tokyo Institute of Technology
• Jack Wells - Oak Ridge National Laboratory
• Si Hammond - Sandia National Laboratories

SC15 Panel Focus for Nov. 17th

Panel Title: Post Moore's Law Computing: Digital versus Neuromorphic versus Quantum

The end of Moore’s Law scaling has sparked research into preserving performance scaling through alternative computational models. This has sparked a debate for the future of computing. Currently, the future of computing is expected to include a mix of quantum, neuromorphic, and digital computing. However, a range of questions remain unanswered for each option.

For example, what problems each approach is most efficient for remains to be determined, and so are issues such as manufacturability, long-term potential, inherent drawbacks, programming, and many others. Can neuromorphic or quantum ever replace digital computing? Can we find alternative CMOS technologies and clever architectures to preserve digital computing performance scaling? What is the upper limit of CMOS?

This is a critical debate for a wide audience, because solving many of tomorrow’s problems requires a reasonable expectation of what tomorrow looks like.

Moderator/Panelist Details:

• George Michelogiannakis (Moderator) - Lawrence Berkeley National Laboratory
• John Shalf - Lawrence Berkeley National Laboratory
• Bob Lucas - University of Southern California
• Jun Sawada - IBM Corporation
• Mattias Troyer - ETH Zurich
• David Donofrio - Lawrence Berkeley National Laboratory
• Shekhar Bokhar - Intel Corporation

Panel Title: Future of Memory Technology for Exascale and Beyond III

Memory technology is in the midst of profound change as we move into the exascale era. Early analysis, including the DARPA UHPC Exascale Report correctly identified the fundamental technology problem as one of enabling low-energy data movement throughout the system.

However, the end of Dennard Scaling and the corresponding impact on Moore’s Law has begun a fundamental transition in the relationship between the processor and memory system. The lag in the increase in the number of cores compared to what Moore’s Law would provide has proven a harbinger of the trend towards memory systems performance dominating compute capability.

Moderator/Panelist Details:

• Richard Murphy (Moderator) - Micron Technology, Inc.
• Shekhar Borkar - Intel Corporation
• Bill Dally - NVIDIA Corporation
• Wendy Elasser - ARM Ltd.
• Mike Ignatowski - Advanced Micro Devices, Inc.
• Doug Joseph - IBM Corporation
• Peter Kogge - University of Notre Dame
• Steve Wallach - Micron Technology, Inc.

Invited Talk Spotlight: Supercomputing, High-Dimensional Snapshots, and Low-Dimensional Models - A Game Changing Computational Technology for Design and Virtual Testing

Aerodynamic analysis of a complete Formula 1 configuration (click on any image to enlarge it).

During the last two decades, giant strides have been achieved in many aspects of computational engineering. Higher-fidelity mathematical models and faster numerical algorithms have been developed for an ever increasing number of applications. Linux clusters are now ubiquitous, GPUs continue to shatter computing speed barriers, and Exascale machines will increase computational power by at least two orders of magnitude.

Coupled fluid-structure analysis of an F-16 Fighting Falcon configuration at high angle of attack.

More importantly, the potential of high-fidelity physics-based simulations for providing deeper understanding of complex systems and enhancing their performance has been recognized in almost every field of engineering. Yet, in many applications, high-fidelity numerical simulations remain so computationally intensive that they cannot be performed as often as needed, or are more often performed in special circumstances than routinely.

High-dimensional solution snapshots of a street car flow problem computed for the purpose of constructing a parametric reduced-order model.

Consequently, the impact of supercomputing on time-critical operations such as engineering design, optimization, control, and test support has not yet fully materialized. To this effect, this talk will argue for the pressing need for a game-changing computational technology that leverages the power of supercomputing with the ability of low-dimensional computational models to perform in real-time.

It will also present a candidate approach for such a technology that is based on projection-based nonlinear model reduction, and demonstrate its potential for parametric engineering problems using real-life examples from the naval, automotive, and aeronautics industries.

Speaker Background:

Invited speaker Charbel Farhat prior to his flight in a F/A-18 Hornet with the legendary Blue Angels.

Charbel Farhat is the Vivian Church Hoff Professor of Aircraft Structures, Chairman of the Department of Aeronautics and Astronautics, and Director of the Army High Performance Computing Research Center at Stanford University. He is a member of the National Academy of engineering, a Fellow of AIAA, ASME, IACM, SIAM, and USACM, and a designated Highly Cited Author in Engineering by the ISI Web of Knowledge.

He was knighted by the Prime Minister of France in the Order of Academic Palms and awarded the Medal of Chevalier dans l’Ordre des Palmes Academiques. He is also the recipient of many other professional and academic distinctions including the Lifetime Achievement Award from ASME, the Structures, Structural Dynamics and Materials Award from AIAA, the John von Neumann Medal from USACM, the Gauss-Newton Medal from IACM, the Gordon Bell Prize and Sidney Fernbach Award from IEEE, and the Modeling and Simulation Award from DoD.

Recently, he was selected by the US Navy as a Primary Key-Influencer, flown by the Blue Angels during Fleet Week 2014, and appointed to the Air Force Science Advisory Board.

 

U.S. Department of Energy Awards $200 Million for Next- Generation Supercomputer at Argonne National Laboratory

From a U.S. Government Press Release:

Under Secretary for Science and Energy Orr Announces Next Steps in Pursuit of Exascale Supercomputing to Accelerate Major Scientific Discoveries and Engineering Breakthroughs.

Argonne, Ill. – Today, U.S. Department of Energy Under Secretary for Science and Energy Lynn Orr announced two new High Performance Computing (HPC) awards that continue to advance U.S. leadership in developing exascale computing.  The announcement was made alongside leaders from Argonne National Laboratory and industry partners at Chicago’s tech start-up hub, 1871.

Under the joint Collaboration of Oak Ridge, Argonne, and Lawrence Livermore (CORAL) initiative, the U.S. Department of Energy (DOE) announced a $200 million investment to deliver a next-generation supercomputer, known as Aurora, to the Argonne Leadership Computing Facility (ALCF). When commissioned in 2018, this supercomputer will be open to all scientific users – drawing America’s top researchers to Argonne National Laboratory. Additionally, Under Secretary Orr announced $10 million for a high-performance computing R&D program, DesignForward, led by DOE’s Office of Science and National Nuclear Security Administration (NNSA).

“Argonne National Laboratory’s announcement of the Aurora supercomputer will advance low-carbon energy technologies and our fundamental understanding of the universe, while maintaining United States' global leadership in high performance computing,” said Under Secretary Orr. “This machine – part of the Department of Energy’s CORAL initiative – will put the United States one step closer to exascale computing.”

Today’s $200 million award is the third, and final, supercomputer investment funded as part of the CORAL initiative, a $525 million project announced by Department of Energy Secretary Moniz in November 2014.  CORAL was established to leverage supercomputers that will be five to seven times more powerful than today’s top supercomputers and help the nation accelerate to next-generation exascale computing.  DOE earlier announced a $325 million investment to build state-of-the-art supercomputers at its Oak Ridge and Lawrence Livermore laboratories.

“Few national investments have the potential to demonstrate dramatic progress and capability across many scientific disciplines and domains with real-world benefits,” said Peter Littlewood, Director, Argonne National Laboratory. “Advanced computing is a lever that drives transformational change in science and technology, accelerating discovery and shortening the time for technology to reach market.”

Key research goals for the Aurora system, expected to be commissioned in 2018 and to which the entire scientific community will have access, include:

• Materials science: Designing new classes of materials that will lead to more powerful, efficient and durable batteries and solar panels.

• Biological science: Gaining the ability to understand the capabilities and vulnerabilities of organisms that can result in improved biofuels and more effective disease control.

• Transportation efficiency: Collaborating with industry to improve transportation systems with enhanced aerodynamics features, as well as enable production of better, more highly-efficient and quieter engines.

• Renewable energy: Engineering wind turbine design and placement to greatly improve efficiency and reduce noise.

The new system, Aurora, will use Intel’s HPC scalable system framework to provide a peak performance of 180 PetaFLOP/s.  The system will help ensure continued U.S. leadership in high-end computing for scientific research while also cementing the nation's position as global leader in the development of next-generation exascale computing systems.  Aurora, in effect a “pre-exascale” system, will be delivered in 2018.  Argonne and Intel will also provide an interim system, called Theta, to be delivered in 2016, which will help ALCF users transition their applications to the new technology.

“The future of high performance computing will require significant innovations on multiple fronts and Argonne's Aurora and Theta supercomputers represent successive generations of the transformation required in future HPC system architectures” said Raj Hazra, Vice President, Data Center Group and General Manager, Technical Computing Group, Intel Corporation. “Working together with Cray, these systems provide a highly flexible and adaptable industry design based on Intel’s HPC scalable system framework that will deliver breakthrough performance, power efficiency and application compatibility through an integrated and balanced system architecture – paving the way for new scientific discoveries and far-reaching benefits on a global scale. Intel is honored to have been awarded the Aurora contract as part of the CORAL program.”

Intel will work with Cray Inc. as the system integrator sub-contracted to provide its industry-leading scalable system expertise together with its proven supercomputing technology and HPC software stack. Aurora will be based on a next-generation Cray supercomputer, code-named “Shasta,” a follow-on to the Cray® XC™ series.

“Cray is honored to partner with Argonne and Intel as we develop our next-generation Shasta system to build one of the fastest supercomputers on the planet for the Department of Energy,” said Peter Ungaro, president and CEO of Cray. “Shasta will be a powerful combination of Intel’s new technologies and Cray’s advanced supercomputing expertise, creating a single, flexible system that will enable huge advances in computing and analytics. Aurora will be the first system in our Shasta family and we couldn’t be more excited.”

In addition to procuring systems like Aurora, the Office of Science and the National Nuclear Security Administration are making longer-term investments in exascale computing under the DesignForward high-performance computing R&D program, designed to accelerate the development of next-generation supercomputers. The program recently awarded $10 million in contracts to AMD, Cray, IBM and Intel Federal, complementing the $25.4 million already invested in the first round of DesignForward. Under this public-private partnership, the four technology firms will work with DOE researchers to study and develop software and hardware technologies aimed at maintaining our nation’s lead in scientific computing.

SC's Jack Dongarra Talks Exascale and Beyond with VR World

Please note: Excerpt approved by VR World.  For the full article, click here.

Dr. Jack Dongarra of Oak Ridge National Laboratory and the University of Tennessee was the SC14 Technical Program Chair and is serving as the SC15 Test of Time Award Co-Chair.

Jack Dongarra, SC15 Test of Time Award Co-Chair

VR World: During your [recent] keynote you mentioned the ‘exascale challenge’. In your opinion, how do we get there from here? What has to happen?

Jack Dongarra: We can’t use today’s technology to build that exascale machine. It would cost too much money, and the power requirements would be way too much. It would take 30 Tianhe-2 clusters in order to get there. We have to have some way to reduce the power and keep the cost under control.

Today, all of our machines are over-provisioned for floating-point. They have an excess floating-point capability. The real issues are related to data movement. It’s related to bandwidth. For example, you have a chip. And this chip has increasing computing capability — you put more cores on it. Those cores need data, and the data has to come in from the sides. You’ve got area that’s increasing due to the computing capability but the perimeter is not increasing to compensate for it. The number of pins limits the data that can go in. That’s the crisis we have.

That has to change. One way it changes is by doing stacking. 3D stacking is a technology that we have at our disposal now. That will allow much more information flow in a way that makes a lot more sense in terms of increasing bandwidth. We have a mechanism for doing that, so we get increased bandwidth. That bandwidth is going to help reduce [power draw] as we don’t have to move data into the chip.

The other thing that’s going to happen is that photonics is going to take over. The data is going to move not over copper lines but over optical paths. The optical paths reduce the amount of power necessary. So that’s a way to enhance the data movement, and to reduce the power consumption of these processors. The chip gets much more affordable, and we can have a chance at turning that computing capability into realized performance — which is a key thing.

In the US, I think we’ll reach exascale in 2022. 2022 is the point where the money will be in place and it’s a question of money. We could build a machine today, but it it would be too expensive. The current thinking is it will be realizable around 2020, and the US is going to be able to deploy the machine in 2022. The money won’t be in place until then, but the technology will be ready ahead of time.

VRW: What’s your take on vendors’ 3D stacking efforts so far?

JD: It’s great. It has to happen. It’s gotta be that way. It’s a natural way to move. It’s going to be the key thing in terms of performance enhancement in the next few years, and being able to effectively employ that as a device. Things look very positive.

VRW: Over the last few years we’ve witnessed China becoming a rising CPU player, with its domestic Alpha and MIPS-based CPUs. Do you have a feeling that conventional CPU vendors have over complicated things for themselves?

JD: China has an indigenous processor which may or may not come out and be deployed in a high performance machine. There are some rumors that the next big machine would be based on the ShenWei CPU. I can understand the motivation for China wanting a processor, they don’t want to be dependent on Western technology for these things. There are some issues here. It’s not going to be on x86 architecture, so software will have to be re-written for this machine. Software is a big deal on these systems, but that can be overcome.

When China does deploy this wide scale, Intel will stand up and take notice. It will be a big thing, now China will be in a position to use their product and not Intel’s product. That becomes a big issue.

End of excerpt. For the full article, click here.